Responsibilities

• Build and manage a team of Field Applications Engineers, providing mentorship, guidance, and technical support to drive customer success and meet business objectives.
• Develop and execute strategies to effectively support customers in the adoption and integration of our IP products.
• Collaborate with sales, marketing, and engineering teams to understand customer requirements, provide technical expertise, and align field activities with overall business goals.
• Build and maintain strong relationships with key customers, understanding their technical needs and challenges, and providing customized solutions and support.
• Drive technical engagements with customers, including pre-sales activities, product demonstrations, technical presentations, and proof-of-concept implementations.
• Serve as a technical point of contact for escalations, providing timely and effective resolution to customer issues, ensuring high customer satisfaction levels.
• Stay up-to-date with industry trends, emerging technologies, and competitive landscape related to CPU IP products, and provide strategic guidance to the team and company leadership.
• Collaborate with product management and engineering teams to provide customer feedback, identify product improvements, and influence the product roadmap.
• Participate in industry conferences, seminars, and technical events to represent the company, showcase our CPU IP products, and establish thought leadership.
• Conduct performance evaluations, provide ongoing training and development opportunities for the FAE team, and ensure a high-performing and motivated workforce.

Requirements

• Bachelor's or Master's degree in Electrical Engineering, Computer Science, or a related field.
• Extensive experience in Field Applications Engineering roles, preferably in CPU IP products, with expertise in Arm or RISC-V.
• Strong technical background in semiconductor technologies, CPU architectures, and system-level understanding.
• Proven experience in managing and leading a team of Field Applications Engineers, driving customer success, and meeting business objectives.
• Willingness to travel to customer sites and industry events as required.

Responsibilities

• Define and establish chip architecture program goals, objectives, and deliverables specific to CPU server and machine learning chip development.
• Collaborate with internal stakeholders, including hardware architects, design teams, software engineers, and product managers, to gather requirements and align on architectural specifications for CPU server and machine learning chips.
• Oversee the chip architecture program in design process, ensuring compliance with industry standards, performance targets, power efficiency, and project timelines.
• Oversee the coordination and integration of CPU server and machine learning chip architectures with system-level designs, software frameworks, and algorithm requirements.
• Manage and track program progress, identifying risks, issues, and dependencies specific to CPU server and machine learning chip development, and implement effective mitigation strategies.
• Communicate program status, updates, and challenges to senior management and stakeholders, highlighting the unique considerations and complexities associated with CPU server and machine learning chip development.
• Foster a collaborative and productive work environment, promoting effective communication, teamwork, and knowledge sharing within the CPU server and machine learning chip development teams.
• Conduct regular program reviews, evaluating performance, identifying areas for improvement, and implementing corrective actions.
• Stay abreast of industry trends, emerging technologies, and advancements in CPU server architectures, machine learning accelerators, and related fields to drive innovation and maintain competitive advantage.

Experience and Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• 7+ years of proven experience in chip architecture design, specifically focused on CPU server and machine learning chips, preferably in a program management or leadership role.
• Strong understanding of server CPU architectures, microarchitecture design, and performance optimization techniques.
• In-depth knowledge of machine learning chip architectures, including accelerators, deep learning processors, or dedicated neural network units (NNUs).
• Familiarity with industry standards, such as x86, ARM, RISC-V, and relevant machine learning frameworks and algorithms.
• Excellent project management skills, with the ability to manage multiple projects simultaneously, while accounting for the unique complexities of CPU server and machine learning chip development.
• Demonstrated experience in leading cross-functional teams and driving collaboration among hardware, software, and algorithm teams.
• Proficiency in project management tools and software.
• Exceptional communication and interpersonal skills, with the ability to effectively communicate complex concepts to technical and non-technical stakeholders.
• Strong problem-solving and decision-making abilities, particularly in addressing challenges specific to CPU server and machine learning chip development.
• Ability to adapt to changing priorities and thrive in a fast-paced, dynamic environment.

Responsibilities

• Design and develop heterogeneous memory architectures for high-performance computing systems, embedded devices, or data center applications.
• Evaluate and select appropriate memory technologies, such as DDR, HBM, GDDR, NVRAM, and emerging non-volatile memory technologies, based on system requirements.
• Define memory subsystem specifications, including capacity, bandwidth, latency, and power requirements, and ensure compliance with industry standards.
• Collaborate with hardware and software teams to optimize memory subsystem performance, including cache coherence, memory hierarchy, and data management.
• Conduct architectural analysis, performance modeling, and simulations to identify bottlenecks and propose design improvements.
• Work closely with vendors and suppliers to assess new memory technologies, evaluate their suitability for specific applications, and negotiate supply agreements.
• Participate in the development of memory controllers, interconnects, and memory management units (MMUs) to ensure efficient memory utilization and data movement.
• Stay up-to-date with the latest advancements in memory technologies, architectures, and industry trends to guide future memory system designs.
• Provide technical guidance and mentorship to junior team members, promoting knowledge sharing and best practices.
• Collaborate with cross-functional teams to define system-level memory requirements, ensuring compatibility with other hardware and software components.

Experience & Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. A Ph.D. is a plus.
• Strong expertise in computer architecture, memory systems, and memory technologies.
• Proven experience in designing and optimizing heterogeneous memory architectures for complex computing systems.
• Proficiency in hardware description languages (HDLs) and simulation tools (e.g., Verilog, SystemVerilog, ModelSim).
• Solid understanding of memory controller designs, cache coherence protocols, and memory management techniques.
• Familiarity with industry-standard memory interfaces and protocols, such as DDR, HBM, GDDR, and PCIe.
• Experience with memory performance analysis, modeling, and simulation tools (e.g., CACTI, RAMulator, DRAMSim).
• Knowledge of emerging memory technologies (e.g., persistent memory, 3D XPoint, MRAM) and their architectural implications.
• Strong problem-solving skills and the ability to analyze complex system-level issues.
• Excellent communication skills and the ability to collaborate effectively with cross-functional teams.

Responsibilities

• Design and develop system-level RAS architectures for complex computing systems, data centers, or mission-critical applications.
• Define and analyze system-level reliability, availability, and serviceability requirements, ensuring compliance with industry standards and customer expectations.
• Collaborate with hardware and software teams to identify potential points of failure, conduct failure mode and effects analysis (FMEA), and propose mitigation strategies.
• Develop fault detection, isolation, and recovery mechanisms to ensure system resilience and minimize downtime.
• Design redundancy and fault-tolerant mechanisms, including redundant components, error correction codes (ECC), and hot-swappable modules, to maximize system availability.
• Define and implement advanced diagnostics and monitoring capabilities to enable proactive system health management and predictive maintenance.
• Evaluate and select appropriate technologies and components to optimize reliability, availability, and serviceability, considering factors such as mean time between failures (MTBF), mean time to repair (MTTR), and total cost of ownership (TCO).
• Collaborate with vendors and suppliers to assess and integrate their RAS-related solutions into the overall system architecture.
• Conduct system-level simulations, analysis, and testing to validate and verify the effectiveness of the RAS architecture and its components.
• Stay up-to-date with the latest advancements in RAS techniques, fault tolerance mechanisms, and industry trends to guide future system designs.

Experience & Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. A Ph.D. is a plus.
• In-depth understanding of the interaction of machine check architecture and error flows with system firmware/software.
• Strong expertise in system-level architecture design, reliability engineering, and fault tolerance mechanisms, optimizing RAS architectures for complex computing systems, data centers, or mission-critical applications.
• Experience with fault-tolerant design principles and techniques, including redundancy, error correction codes (ECC), and error recovery mechanisms.
• Proficiency in system-level simulation tools and methodologies (e.g., fault injection, reliability block diagrams, failure rate analysis).
• Excellent problem-solving skills, attention to detail, and the ability to analyze complex system-level issues.
• Knowledge of industry standards and best practices related to reliability, availability, and serviceability (e.g., ISO 26262, IEC 61508, MIL-STD-2167A) is a plus
• Strong communication and collaboration skills to work effectively with cross-functional teams.
• Prior experience on post silicon reliability analysis.

Responsibilities

• Design complex PCB layouts from initial placement, SI and PI optimization in tandem with the team, as well as vendor signoffs and production release.
• Create design specs, liaise with vendors and drive new technology adoption.
• Support SI and PI simulations and iteratively improve our best practices.
• Contribute to design and sign-off with ASIC packaging teams both internal and external, ODM partners and internal layout teams.
• Participate in design reviews, providing valuable input from your area of expertise and beyond.
• Document design processes and provide training to other team members as necessary.

Experience & Qualifications

• Bachelor's degree in Electrical Engineering or equivalent, with 5+ years of experience in high speed PCB layout design.
• Significant experience in high speed PCB or package design, at least 10Gbps (100GbE, GDDR6, PCIe Gen5+, etc..).
• Familiarity with the ASIC packaging design flow a bonus.
• Exposure to high speed performance metrics, ICR, ERL, COM, NEXT and FEXT is a bonus.
• Well versed in all the latest and greatest features in ECAD tools, tabbed routing, HDI, weave effects.
• Expert in the Cadence Allegro environment, constraints entry, and high speed design.
• Strong problem-solving skills and an ability to think critically.
• Excellent written and verbal communication skills.

Responsibilities

• Define PD requirements by working closely with the front-end team, understand the chip architecture and drive physical aspects early in the design cycle
• Physical design tasks including such as synthesis, PnR, timing closure, area improvement, floorplanning, clocking, I/O planning and power optimization
• Discussions with 3rd party IP providers, foundry partners and design services
• End to end tasks from flow development to sign-off
• Deploy innovative techniques for improving power, performance and area of the design, drive experiments with RTL, and evaluate synthesis, timing and power results

Experience & Qualifications

• BS/MS/PhD in EE/ECE/CE/CS
• Hands-on experience with synthesis, block and chip level implementation with industry standard PnR flows and tools
• Strong experience in SOC/ASIC/GPU/CPU design flows on taped out designs, expertise in timing closure at block/chip levels and ECO flows
• Experience with back-end design tools such as Primetime, Innovus, RedHawk, etc.
• Knowledge of low-power design flows such as power gating, multi-Vt and voltage scaling
• Strong programming skills in Tcl/Perl/Shell/Python
• Excellent understanding of logic design fundamentals and gate/transistor level implementation
• Exposure to DFT is an asset
• Prior experience working on high performance technology nodes and understanding of deep sub-micron design problems/solutions
• Strong problem solving and debug skills across various levels of design hierarchies

Responsibilities

• Work closely with physical design team and tool vendors to define flow requirements
• Flow tasks may include enabling targets such as floor-planning, synthesis, PnR, timing and phy closure
• Optimize and support PnR flow to ensure quality results on schedule
• Discussions with vendor tool providers, foundry partners and design services
• End to end tasks from flow development to sign-off
• Deploy innovative techniques for improving power, performance and area of the design, drive experiments with PD, and evaluate PnR, timing and power results

Experience & Qualifications

• BS/MS/PhD in EE/ECE/CE/CS
• Hands-on experience with synthesis, block and chip level implementation with industry standard PnR flows and tools
• Strong experience in SOC/ASIC/GPU/CPU design flows on taped out designs, expertise in timing closure at block/chip levels and ECO flows
• Experience with back-end design tools such as Primetime, Innovus, RedHawk, etc.
• Knowledge of low-power design flows such as power gating, multi-Vt and voltage scaling
• Strong programming skills in Tcl/Perl/Shell/Python
• Excellent understanding of logic design fundamentals and gate/transistor level implementation
• Exposure to DFT is an asset
• Prior experience working on high performance technology nodes and understanding of deep sub-micron design problems/solutions
• Strong problem solving and debug skills across various levels of design hierarchies

Responsibilities

• Build simulation models of the package and chiplet complexes.
• Collaborate with cross-functional teams from Silicon Architecture to PCB and System Integration.
• Design monolithic and 2.5D package interconnects using Cadence APD (mentorship will be provided).
• Utilize industry-standard simulation tools to optimize power distribution networks and high-speed channels between chiplets.
• Develop automation routines for design and simulation

Qualifications

• Fundamental understanding of Signal Integrity and Power Integrity
• Familiarity with ANSYS and/or Cadence tools for SIPI and Routing
• Ability to break complex problems into small
• Ability to deal with ambiguity and come up with creative solution

Responsibilities

• Define PD requirements by working closely with the front-end team, understand the chip architecture and drive physical aspects early in the design cycle
• Physical design tasks such as synthesis, PnR, timing closure, area improvement, floorplanning, clocking, I/O planning and power optimization
• Discussions with 3rd party IP providers, foundry partners and design services
• End to end tasks from flow development to sign-off
• Deploy innovative techniques for improving power, performance and area of the design, drive experiments with RTL, and evaluate synthesis, timing and power results

Experience & Qualifications

• BS/MS/PhD in EE/ECE/CE/CS
• Hands-on experience with synthesis, block and chip level implementation with industry standard PnR flows and tools
• Strong experience in SOC/ASIC/GPU/CPU design flows on taped out designs, expertise in timing closure at block/chip levels and ECO flows
• Experience with back-end design tools such as Primetime, Innovus, RedHawk, etc.
• Knowledge of low-power design flows such as power gating, multi-Vt and voltage scaling
• Strong programming skills in Tcl/Perl/Shell/Python
• Excellent understanding of logic design fundamentals and gate/transistor level implementation
• Exposure to DFT is an asset
• Prior experience working on high performance technology nodes and understanding of deep sub-micron design problems/solutions
• Strong problem solving and debug skills across various levels of design hierarchies

Responsibilities

• Work closely with physical design team and tool vendors to define flow requirements
• Flow tasks may include enabling targets such as floor-planning, synthesis, PnR, timing and phy closure
• Optimize and support PnR flow to ensure quality results on schedule
• Discussions with vendor tool providers, foundry partners and design services
• End to end tasks from flow development to sign-off
• Deploy innovative techniques for improving power, performance and area of the design, drive experiments with PD, and evaluate PnR, timing and power results

Experience & Qualifications

• BS/MS/PhD in EE/ECE/CE/CS with at least 5 years of industry experience
• Hands-on experience with synthesis, block and chip level implementation with industry standard PnR flows and tools
• Strong experience in SOC/ASIC/GPU/CPU design flows on taped out designs, expertise in timing closure at block/chip levels and ECO flows
• Experience with back-end design tools such as Primetime, Innovus, RedHawk, etc.
• Knowledge of low-power design flows such as power gating, multi-Vt and voltage scaling
• Strong programming skills in Tcl/Perl/Shell/Python
• Excellent understanding of logic design fundamentals and gate/transistor level implementation
• Exposure to DFT is an asset
• Prior experience working on high performance technology nodes and understanding of deep sub-micron design problems/solutions
• Strong problem solving and debug skills across various levels of design hierarchies

Responsibilities

• Define PD requirements by working closely with the front-end team, understand the chip architecture and drive physical aspects early in the design cycle
• Physical design tasks such as synthesis, PnR, timing closure, area improvement, floorplanning, clocking, I/O planning and power optimization
• Discussions with 3rd party IP providers, foundry partners and design services
• End to end tasks from flow development to sign-off
• Deploy innovative techniques for improving power, performance and area of the design, drive experiments with RTL, and evaluate synthesis, timing and power results

Experience & Qualifications

• BS/MS/PhD in EE/ECE/CE/CS
• Hands-on experience with synthesis, block and chip level implementation with industry standard PnR flows and tools
• Strong experience in SOC/ASIC/GPU/CPU design flows on taped out designs, expertise in timing closure at block/chip levels and ECO flows
• Experience with back-end design tools such as Primetime, Innovus, RedHawk, etc.
• Knowledge of low-power design flows such as power gating, multi-Vt and voltage scaling
• Strong programming skills in Tcl/Perl/Shell/Python
• Excellent understanding of logic design fundamentals and gate/transistor level implementation
• Exposure to DFT is an asset
• Prior experience working on high performance technology nodes and understanding of deep sub-micron design problems/solutions
• Strong problem solving and debug skills across various levels of design hierarchies

Responsibilities

• Administration and automation of workflows associated with servers, batch compute infrastructure and licensing tools
• Linux administration for design team’s compute infrastructure
• Development and maintenance of containers used across the design team
• VM hosting and management for critical design team services
• Maintain and enhance the Git infrastructure to support CI/CD, nightly regressions across multiple development platforms
• Build software tools and scripts for design flow automation
• Engage with leading industry vendors and 3rd party IP providers, driving integration of external tools and IPs in the design flow
• Experience with open-source tool-flows and deployment of applicable tools and infrastructure in the design flow; drive tool decisions for build vs leverage vs buy

Experience & Qualifications

• BS/MS/PhD in EE/ECE/CE/CS with minimum 3 years of industry experience
• Experience with HPC compute
• Experience with development of DV tools and infrastructure and large-scale regression environments is required, extensive debug of automation workflows
• Experience working with build tools such as Bazel
• Knowledge of EDA tools, strong understanding of simulators. Hands-on experience working with emulation environment and tools is a plus
• Expertise developing tools for revision control, prior experience with git preferred
• Very strong programming skills in C/C++, scripting skills in Python, Tcl, Perl
• Familiarity with relational databases (e.g MySql, MariaDB) and visualization tools (e.g.Kibana)

Responsibilities

• RTL coding for implementing features and logic design for CPU block
• Understand and debug RTL code for the CPU and help make changes to the design
• Help with development of architectural tools for ISA level verification
• Write C/assembly based stimulus that scales from pre-silicon to emulation and post-silicon domain
• Help with infrastructure and tool development for RTL, Performance and DV environments
• Support development and integration of testbench components such as microarchitectural models, checkers and coverage

Experience & Qualifications

• Senior year BS/MS or PhD candidate in EE/ECE/CE/CS with a strong GPA
• Prior academic work in the field of computer architecture, internship experience preferred
• Academic projects in C++ / SV / UVM as well knowledge of scripting languages
• Understanding of assembly level programming
• Knowledge of hardware description languages (Verilog, VHDL)
• Strong academic skills or internship experience in verification methodologies and techniques – Simulation/debug, TB development, stimulus, checking, coverage
• Strong problem solving and analytical skills

Responsibilities

• Lead functional and performance verification of the load store unit for a from-scratch high performance CPU while working closely with Architecture and RTL team
• Develop detailed block level verification plans for load store that includes both architectural (RISCV ISA) and microarchitectural functionality
• Design and develop reusable block level testbench components in SV, UVM and C++, that include microarchitectural models, monitors, checkers
• Develop random and directed stimulus that spans pre-silicon, emulation and post-silicon domain
• Evaluate and integrate open-source toolchains into the DV flow
• Develop DV environment, tools and infrastructure to enable functional verification for pre-silicon, emulation and post-silicon
• Work with design, test and post silicon validation teams to ensure high quality delivery of the load store block

Experience & Qualifications

• BS/MS/PhD in EE/ECE/CE/CS with at least 8 years of experience
• Strong background and experience with high performance OOO CPU microarchitecture especially with load/store, caches and memory subsystem
• Experience working on an x86, ARM or RISCV based CPU
• Architectural understanding of address translation, memory ordering, cache cohereney protocols, memory consistency and multi-processors
• Significant experience debugging RTL and DV in a simulation environment
• Verification methodologies and techniques – Simulation/debug, TB development, stimulus, checking, coverage, infrastructure, tools
• Experience with C++ / SV / UVM as well as scripting languages
• Experience with hardware description languages (Verilog, VHDL) and simulators (VCS, NC, Verilator)
• Strong problem solving and debug skills across various levels of design hierarchies

Responsibilities

• Define Design for Debug requirements for a from-scratch high performance and architect the overall debug capabilities and infrastructure
• Develop detailed microarchitecture for debug and trace logic for a server class CPU based on RISCV ISA
• RTL coding in Verilog leveraging on both industry tools as well as open-source infrastructure
• Work with design, test and post silicon validation teams to deploy debug features
• Drive trade-offs for your logic by working closely with performance, DV and physical design engineers to craft optimal solutions that meet the design goals
• Deploy innovative techniques for improving power, performance and area of the design, drive experiments with RTL and evaluate synthesis, timing and power results
• Debug RTL/logic issues across various hierarchies (core, chip) in both pre-silicon and post-silicon environment
• Enhance RTL design environment, tools and infrastructure

Experience & Qualifications

• BS/MS/PhD in EE/ECE/CE/CS with at least 5 years of experience
• Experience with Debug, Trace, JTAG and other design for debug (DFD) domains for an x86, ARM or RISCV based CPU
• Experience with computer architecture/system components/network/fabrics as a part of a CPU, ASIC or SOC design team
• Expertise in logic design and ability to evaluate functional, performance, timing and power for you design
• Strong experience with hardware description languages (Verilog, VHDL) and simulators (VCS, NC, Verilator)
• Expertise in microarchitecture definition and specification development
• Prior experience in industry standard ISAs – ARM, RISC-V, X86 preferred
• Strong problem solving and debug skills across various levels of design hierarchies

Responsibilities

• Drive formal verification for multiple CPU blocks by putting together formal test plans and executing on them
• Create formal verification flows and deploy techniques that leverage on both industry standard and open-source tools. Drive automation of formal testbenches and ensure they are a part of regressions
• Develop assertions, cover properties and connectivity checks as a part of formal verification flows and debug any failures in RTL regressions
• Deploy scripts and automation to support formal, review setups and proofs with Microarchitecture and DV engineers

Experience & Qualifications

• BS/MS/PhD in EE/ECE/CE/CS with at least 5 years of experience
• Prior experience with formal verification methods and techniques
• Strong knowledge of computer architecture with some experience on CPU, GPU, Cache designs
• Hands-on experience with formal verification tools such as Jasper, VC-Formal, Yosys, IFV, Questa, etc.
• Proficiency in programing/scripting languages
• Strong experience with hardware description languages (Verilog, VHDL) and simulators (VCS, NC, Verilator), experience capturing design specification in a temporal assertion language such as SVA
• Strong problem solving and debug skills for complex logic and digital designs

Responsibilities

• Functional and performance verification of the Mid Core unit for a from-scratch high performance CPU while working closely with Architecture and RTL team
• Develop detailed block level verification plans for Mid Core that includes both architectural (RISCV ISA) and microarchitectural functionality
• Design and develop reusable block level testbench components in SV, UVM and C++, that include microarchitectural models, monitors, checkers
• Develop random and directed stimulus that spans pre-silicon, emulation and post-silicon domain
• Evaluate and integrate open-source toolchains into the DV flow
• Develop DV environment, tools and infrastructure to enable functional verification for pre-silicon, emulation and post-silicon
• Work with design, test and post silicon validation teams to ensure high quality delivery of the MidCore block

Experience & Qualifications

• BS/MS/PhD in EE/ECE/CE/CS with at least 3 years of experience
• Strong background and experience with high performance OOO CPU microarchitecture
• Experience working on an x86, ARM or RISCV based CPU
• Architectural understanding of Rename, Scheduler, Reorder Buffer and Datapath for an Out of Order CPU
• Significant experience debugging RTL and DV in a simulation environment
• Verification methodologies and techniques – Simulation/debug, TB development, stimulus, checking, coverage, infrastructure, tools
• Experience with C++ / SV / UVM as well as scripting languages
• Experience with hardware description languages (Verilog, VHDL) and simulators (VCS, NC, Verilator)
• Strong problem solving and debug skills across various levels of design hierarchies

Responsibilities:

• Lead the development and execution of comprehensive verification plans for complex digital designs, ensuring thorough testing of functionality, performance, and compliance with specifications.
• Define and drive the verification strategy, methodologies, and best practices across projects.
• Collaborate with design, architecture, and software teams to understand design requirements and specifications.
• Guide and mentor junior verification engineers, providing technical leadership and fostering their growth.
• Develop advanced verification environments using industry-standard methodologies and languages (e.g., SystemVerilog, UVM).
• Create and execute testbenches, test cases, and coverage plans to ensure complete verification coverage.
• Analyze and debug complex functional and performance issues, working closely with design teams to resolve them.
• Contribute to continuous improvement of verification processes, methodologies, and tools.
• Collaborate with cross-functional teams to drive seamless integration of verified designs into larger systems.
• Stay updated with the latest advancements in design verification methodologies, tools, and industry trends.
• Participate in design reviews, offering valuable insights to improve design quality and verification completeness.

Experience and Qualifications:

• Bachelor's, Master's, or Ph.D. degree in Electrical Engineering, Computer Engineering, or a related field with a minimum of 15 years of industry experience.
• Proven track record of leading successful design verification efforts for complex digital designs.
• Expertise in verification methodologies such as UVM (Universal Verification Methodology).
• Proficiency in SystemVerilog and other industry-standard verification languages.
• Strong understanding of digital design, computer architecture, and microarchitecture concepts.
• Experience with verification tools and simulators, such as Questa, VCS, or similar.
• Excellent problem-solving skills and the ability to analyze and debug intricate design issues.
• Leadership experience, with the ability to mentor and guide junior verification engineers.
• Effective communication skills and the ability to collaborate in cross-functional teams.
• Knowledge of scripting languages (e.g., Python, Perl) for testbench automation is a plus.
• Familiarity with formal verification methodologies is an advantage.

Responsibilities:

• Lead the design and implementation of high-performance digital circuits using RTL (Register Transfer Level) design methodologies.
• Collaborate with cross-functional teams to define architecture, specifications, and design constraints for new projects.
• Drive the development of efficient and optimized RTL code while considering power, performance, and area (PPA) trade-offs.
• Utilize industry-standard tools and methodologies for RTL design, simulation, and synthesis.
• Contribute to verification efforts, ensuring designs meet functional and performance specifications through simulation and other validation techniques.
• Mentor and guide junior engineers, providing technical leadership and fostering their professional growth.
• Collaborate with physical design, software, and system teams to achieve seamless integration and successful product realization.
• Stay current with the latest advancements in digital design methodologies, tools, and industry trends.
• Participate in design reviews, offer valuable insights, and provide solutions to complex design challenges.

Experience and Qualifications:

• Bachelor's, Master's, or Ph.D. degree in Electrical Engineering, Computer Engineering, or a related field and at least 15 years of industry experience.
• Proven track record of leading and successfully delivering complex digital designs from concept to production.
• Extensive experience with RTL design, including Verilog and/or VHDL.
• Proficiency in using industry-standard EDA tools for design, simulation, synthesis, and verification.
• Strong understanding of computer architecture, microarchitecture, and system-level considerations.
• In-depth knowledge of ASIC and FPGA design methodologies.
• Excellent problem-solving skills and the ability to analyze and debug intricate design issues.
• Effective communication skills and the ability to work collaboratively in cross-functional teams.
• Leadership experience, with the ability to mentor and guide junior engineers.
• Publications, patents, or contributions to industry forums demonstrating thought leadership are a strong advantage.

Responsibilities:

• Develop and execute detailed verification plans for power management features, ensuring comprehensive coverage of functionality and performance.
• Collaborate closely with design, architecture, and software teams to understand power management requirements and specifications.
• Create advanced verification environments using industry-standard methodologies and languages (e.g., SystemVerilog, UVM) to test power management features.
• Design and implement testbenches, test cases, and coverage plans specific to power management verification.
• Develop power-aware simulations to analyze power consumption under different operational scenarios.
• Work closely with physical design and power management teams to validate the implementation of power-saving techniques.
• Analyze and debug complex functional and performance issues related to power management.
• Contribute to the development of verification tools and methodologies, improving efficiency and accuracy.
• Collaborate with cross-functional teams to ensure seamless integration of verified power management features.
• Stay updated with the latest advancements in power management verification methodologies, tools, and industry trends.
• Participate in design reviews, offering insights on power management verification strategies.

Experience & Qualifications

• Bachelor's, Master's, or Ph.D. degree in Electrical Engineering, Computer Engineering, or a related field with a minimum of 5 years of industry experience.
• Proven track record in design verification with a focus on power management features.
• Expertise in verification methodologies such as UVM (Universal Verification Methodology).
• Proficiency in SystemVerilog and other industry-standard verification languages.
• Strong understanding of digital design, power management techniques, and low-power design principles.
• Experience with verification tools and simulators, such as Questa, VCS, or similar.
• Familiarity with power formats such as UPF (Unified Power Format) for specifying power intent is advantageous.
• Excellent problem-solving skills and the ability to analyze power management issues.
• Effective communication skills and the ability to collaborate in cross-functional teams.
• Knowledge of scripting languages (e.g., Python, Perl) for testbench automation is a plus.
• Prior experience in CPU or RISCV architecture] related to power management verification is advantageous.

Responsibilities

• RTL design and Microarchitecture of the Core unit for a from-scratch high performance CPU based on RISCV ISA, working closely with the DV and PD team RTL coding in Verilog leveraging on both industry tools as well as open-source infrastructure
• Work with design, test and post silicon validation teams for high quality delivery.
• Drive trade-offs for your logic by working closely with performance, DV and physical design engineers to craft optimal solutions that meet the design goals
• Deploy innovative techniques for improving power, performance and area of the design, drive experiments with RTL and evaluate synthesis, timing and power results
• Debug RTL/logic issues across various hierarchies (core, chip) in both pre-silicon and post-silicon environment
• Enhance RTL design environment, tools and infrastructure

Experience & Qualifications

• BS/MS/PhD in EE/ECE/CE/CS with at least 5 years of industry experience
• Strong background and experience with high performance OOO CPU microarchitecture
• Experience working on an x86, ARM or RISCV based CPU
• Architectural understanding of Rename, Scheduler, Reorder Buffer and Datapath for an Out of Order CPU
• Expertise in logic design and ability to evaluate functional, performance, timing and power for you design
• Strong experience with hardware description languages (Verilog, VHDL), simulators (VCS, NC, Verilator), Synthesis and Power tools
• Expertise in microarchitecture definition and specification development
• Strong problem solving and debug skills across various levels of design hierarchies

Responsibilities:

• Lead the development of power management strategies for complex digital designs, ensuring optimal power consumption without compromising performance.
• Collaborate closely with design, architecture, and software teams to define power management requirements and strategies.
• Utilize industry-standard tools and methodologies to perform power analysis and estimate power consumption at different stages of design.
• Implement power-saving features at the RTL level, such as clock gating, voltage scaling, and dynamic power management.
• Develop and implement low-power design techniques, considering trade-offs between power, performance, and area (PPA).
• Analyze power profiles and identify opportunities for further power reduction through design optimization.
• Create and maintain power management documentation, guidelines, and best practices for the engineering team.
• Mentor and guide junior engineers, sharing your expertise in power-efficient design techniques.
• Collaborate with physical design and verification teams to ensure the successful implementation of power management features.
• Stay up-to-date with the latest advancements in power management methodologies, tools, and industry trends.
• Participate in design reviews, offering insights on power-related considerations and solutions.

Experience and Qualifications:

• Bachelor's, Master's, or Ph.D. degree in Electrical Engineering, Computer Engineering, or a related field and a minimum of 5 years of industry experience.
• Proven track record of successfully optimizing power consumption in complex digital designs.
• Expertise in RTL design and strong understanding of power management techniques.
• Proficiency in industry-standard EDA tools for power analysis, simulation, and verification.
• Familiarity with low-power design languages such as UPF (Unified Power Format) is a plus.
• Strong analytical skills and the ability to analyze power profiles and optimize designs accordingly.
• Effective communication skills and the ability to work collaboratively in cross-functional teams.
• Leadership experience, with the ability to mentor and guide junior engineers.

Responsibilities

• Architecture of Tenstorrent's IP blocks including aggressive optimization for performance, power as well as area
• Implementation of Tenstorrent IP and SOC RTL logic in Verilog
• Occasional verification of Tenstorrent's IP and SOC logic, using advanced verification methodologies - UVM, FPGA prototyping, and emulation
• Performance and power verification and validation of Tenstorrent's IP and SOC

Experience & Qualifications

• Bachelor/Master in Electrical/Computer Engineering/Engineering Science
• Expert knowledge of Hardware Description Languages (Verilog/VHDL)
• Deep and broad understanding of processor/computer architecture
• Knowledge and understanding of the full ASIC design flow, including synthesis, P&R
• Excellent programming skills. C/C++ as well as scripting languages (Perl, tcl)
• Experience with high frequency logic design, scalar and vector processor architecture, GPU architecture and programming models, digital signal processing hardware, SoC architecture, memory subsystem architecture, real time hardware/firmware systems or deep learning is very beneficial

Responsibilities

• Verification of Tenstorrent's digital IP and SOC logic, using advanced verification methodologies - UVM, FPGA prototyping, emulation
• Creation of test plans
• Writing testbenches, checkers and tests, models, assertions and irritators
• Creating functional coverage points
• Reviewing verification results and metrics and, driving the verification convergence towards tape-out
• Performance and power verification and validation of Tenstorrent's IP and SOC

Experience & Qualifications

• Bachelor/Master in Electrical/Computer Engineering/Engineering Science
• Expert in hardware verification languages (SystemVerilog, SystemC)
• Experience with UVM and coverage driven constrained random verification
• Experience with Low power verification techniques
• Excellent programming skills. C/C++ as well as scripting languages (Perl, tcl)
• Deep interest in computer architecture, under-the-hood details of machine learning frameworks, GPU programming and methods for efficient parallelization of deep learning execution

Responsibilities

• Work with the IP R&D team to test the IP drops, generate the IP collaterals, test the SW releases, create the technical documentation including integration guide, programming guide and packaging the IP for customer drops.
• Interface between customers and R & D to escalate requests for improvements and provide a good understanding of customer needs
• Owns all customer technical issues, utilizing all available resources to resolve those issues and achieve customer production.
• Helps customers with module level and system-level integration issues, providing local technical and logistical support to insure successful adoption
• Be a strong advocate for customer success within Tenstorrent

Experience & Qualifications

• 5-10 years of experience in designing or developing IPs and SoC (System on Chip)
• Relevant front-end digital IP and ASIC design experience, from RTL, Verification to synthesis
• Working knowledge of SoC architecture, including CPU, Interfaces (from JTAG to AMBA), Fabric (Arteris and AXI) and other IP integration, DDR, optimization techniques to achieve power, performance and area goals.
• Experience with IP frontend CAD tools (Lint, CDC, Simulation) and backend tools (Synthesis, Equivalence/FEV, Timing, Place and route)
• Familiar with the entire chip development process including DFT (scan insertion, MBIST and LBIST), floor-planning, timing closure, power estimation, IR analysis, etc.
• Knowledge of Functional Safety requirements
• Knowledge of UVM, Makefiles, BASH, Python, C/C++, and DPI
• Knowledge of product engineering methodologies
• Knowledge of IP test methodologies
• Strong debugging, troubleshooting and crisis management skills
• Customer focused and enjoy working with them to help find solutions
• Experience in a customer facing role and/or working with a sales team
• Highly motivated, excellent problem solver and results-driven
• Good presentation, documentation and organizational skills
• BS Electrical Engineering, Computer Engineering or Computer Science. Master’s degree is a plus.

Responsibilities

• Design, develop, and maintain the cloud-based infrastructure to support our semiconductor startup.
• Collaborate with cross-functional teams to gather requirements and translate them into scalable cloud solutions.
• Implement and maintain the company's cloud portal, providing a user-friendly interface for managing cloud resources.
• Configure and optimize Kubernetes (K8) clusters to support efficient deployment and management of containerized applications.
• Manage and maintain the OpenStack infrastructure, ensuring high availability and scalability.
• Automate infrastructure provisioning processes, including both cloud and bare metal resources, using industry-standard tools and technologies such as Python, Ansible, and C++.
• Develop systems-level software to interface with hardware components, optimizing performance and reliability.
• Monitor and troubleshoot cloud-based systems, addressing any performance or security issues.
• Stay up to date with emerging cloud technologies, systems software, and industry trends, providing recommendations for continuous improvement.
• Participate in code reviews, ensuring high-quality code and adherence to best practices.

Experience & Qualifications

• Bachelor's or Master's degree in Computer Science, Software Engineering, or a related field.
• Proven experience as a software engineer with a focus on cloud-based infrastructure.
• Strong expertise in designing and deploying cloud solutions using Portal, Kubernetes (K8), and OpenStack.
• Experience with infrastructure provisioning tools such as Terraform, Ansible, or Chef.
• Proficiency in programming languages like Python, C++, and scripting languages like Bash.
• Familiarity with bare metal provisioning, including hardware configurations and low-level systems software development.
• Understanding of security best practices in cloud environments.
• Excellent problem-solving and analytical skills.
• Strong communication and collaboration abilities, with the capability to work effectively in cross-functional teams.
• Self-motivated and able to work independently with minimal supervision.

Responsibilities

• Make sure continuous integration (CI) for our SDK performs smoothly
• Monitor CI tests dashboard
• Report CI tests failures (issues in product code, test code, test running infra, and machine health)
• Triage, mitigate, and fix some of the CI test failures (Area owning teams fixes most of failures)
• Report quality state of SDK code based on CI tests dashboard
• Report top issues in CI tests running infrastructure
• Manage releasing SDK to Tenstorrent’s cloud and other customers
• Suggest git commit ids for snaps to SDK’s release branch based on CI tests dashboard
• Monitor release tests dashboard
• Report regressions and validate fixes pushed to the release branch
• Sign-off quality and package SDK releases

Experience and Qualifications

• Degree in Computer Science, Computer Engineering, Electronics, or Math is mandatory.
• Experience in scripting, e.g. using Python or GNU/Linux Bash is mandatory.
• Experience in supporting cloud services in SRE-like or DevOps-like roles is a plus.
• Deep interest in modern neural networks, AI/ML SDKs, and systems is a plus.

Responsibilities

• Develop machine learning graph compiler
• Participate in the co-design of Tenstorrent's hardware and software stack
• Benchmark, analyze, and optimize performance of key machine learning applications across Tenstorrent's hardware and software stack
• Develop performance analysis and estimation infrastructure that feeds into Tenstorrent compiler
• Develop high-performance run-time engine
• Integrate the Tenstorrent software into leading machine learning frameworks
• Work closely with machine learning engineers to discover the hardware and software requirements of current and future machine learning applications

Experience & Qualifications

• BSc, MSc or PhD in Electrical/Computer Engineering or Computer Science
• 7+ years of experience with algorithms, data structures, and software development in C/C++. Python expertise is welcome as well
• Familiarity with and passion for any of the following -- machine learning, compilers, parallel programming, high-performance and massively parallel systems, processor and computer architecture -- is a plus

Responsibilitiesz

• Develop machine learning graph compiler
• Benchmark, analyze, and optimize performance of key machine learning applications across Tenstorrent's hardware and software stack
• Develop performance analysis and estimation infrastructure that feeds into Tenstorrent compiler
• Integrate the Tenstorrent software into leading machine learning frameworks
• Work closely with machine learning engineers to discover the hardware and software requirements of current and future machine learning applications

Experience & Qualifications

• BSc, MSc or PhD in Electrical/Computer Engineering or Computer Science
• Familiarity with common AI/ML models, and basics of machine learning operations (matrix multiplications, convolutions, etc.)
• Experience with algorithms, data structures, and software development in C/C++.
• Expertise in Python.
• Familiarity with and passion for any of the following -- machine learning, compilers, parallel programming, high-performance and massively parallel systems, processor and computer architecture -- is a plus

Responsibilities

• Develop machine learning graph compiler
• Participate in the co-design of Tenstorrent's hardware and software stack
• Benchmark, analyze, and optimize performance of key machine learning applications across Tenstorrent's hardware and software stack
• Develop performance analysis and estimation infrastructure that feeds into Tenstorrent compiler
• Develop high-performance run-time engine
• Integrate the Tenstorrent software into leading machine learning frameworks
• Work closely with machine learning engineers to discover the hardware and software requirements of current and future machine learning applications

Experience & Qualifications

• BSc, MSc or PhD in Electrical/Computer Engineering or Computer Science
• Experience with algorithms, data structures, and software development in C/C++. Python expertise is welcome as well
• Familiarity with and passion for any of the following -- machine learning, compilers, parallel programming, high-performance and massively parallel systems, processor and computer architecture -- is a plus

Responsibilities

• Develop machine learning graph compiler
• Implement core components of the compiler – graph transformation passes, place & route, and other optimizations
• Participate in the co-design of Tenstorrent's hardware and software stack
• Work closely with machine learning engineers to discover the hardware and software requirements of current and future machine learning applications

Experience & Qualifications

• BSc, MSc or PhD in Electrical/Computer Engineering or Computer Science
• Experience with algorithms, data structures, and software development in C/C++ and Python
• Familiarity with and passion for any of the following -- machine learning, compilers, parallel programming, high-performance and massively parallel systems, processor and computer architecture

Responsibilities

• 
  
Technical Program Leadership:
• Oversee, lead and manage cross-functional software engineering teams working on compilers, performance optimization, AI models, and cloud integration.
• Define and track clear goals, priorities, and milestones, ensuring alignment with overall Tenstorrent’s corporate goals.
• Provide Programmatic guidance, mentorship, and foster a culture of execution within SW teams
End-to-End Software Development Life Cycle:
• Improve and execute on software development life cycles that encompass feature development, bug resolution, quality metrics, and risk mitigation.
• Collaborate with engineering, test, and customer teams to establish metrics, testing frameworks, and release processes.
Strategic Leadership and resolving ambiguity:
• Devise strategic roadmap, product definition and program metrics with internal and external stakeholders, and leadership
• Monitor project progress, identify risks, and proactively implement mitigation strategies.
Stakeholder management & Strategic leadership:
• Foster effective collaboration between Software, Hardware, Customer, Operations, Cloud and other cross-functional AI and Compute teams.
• Communicate complex technical concepts clearly across executive and engineering stakeholders.
Technical Expertise:
• Leverage your expertise in software development, AI models, compilers, performance optimization, and cloud integration to make informed decisions and promote innovation.
• Stay abreast of industry trends, emerging technologies, and best practices to ensure our AI and Compute solutions remain at the forefront of the industry.

Experience & Qualifications

• BS in Computer Science, Electrical Engineering, or a related technical field; MS/MBA preferred
• 5+ years of Technical program management in Software, Embedded, Semiconductor, or AI domains
• Strong understanding of hardware/software co-design principles, and experience working with cross-functional teams of developers, test, and Field-Application-Engineering.
• Exceptional Program management skills, including the ability to manage multiple programs, prioritize tasks, influence teams and adapt to changing priorities.
• Excellent communication and interpersonal skills, with the ability to collaborate effectively across teams and communicate complex technical concepts.
• Strong analytical and problem-solving abilities, with a proactive approach to identifying and mitigating risks.
• Strong experience and devising metrics, roadmaps, dashboards and preparing executive level presentations
• Experience with project & program management tools and methodologies (e.g., Agile, Scrum, JIRA).
• PMP, PgMP, or other relevant project/program management certifications are a plus.

Responsibilities

• Help envision and build the future of our data platform. You will have a remarkable impact on the overall tech stack we use to process the rich data available at Tenstorrent.
• Design and implement end-to-end data pipelines to process batch and streaming data at scale, employing cutting-edge data processing and orchestration methodologies, including distributed computing solutions when applicable.
• Lead the integration of a wide range of technologies constituting our data infrastructure. Architect and build new ones when available solutions fall short.
• Identify, evolve, and champion data/software engineering best practices.
• Help define and implement scalable data governance, security and privacy solutions, including an AI-powered data catalog.
• Build automation for CI/CD, IaC and containerization.
• Contribute to our data engineering roadmap, working cross-functionally to define priorities.

Experience & Qualifications

• Excellent Python programming skills, with a focus on data processing.
• Experience designing, managing and optimizing SQL databases and schemas.
• Advanced SQL queries and functions programming.
• Experience working with no-SQL and time-series databases.
• Experience building RESTful APIs.
• Proficiency in containerization technologies.
• Experience building automated CI/CD pipelines.
• Experience working with AWS.
• Familiarity with IaC technologies.
• Familiarity with gRPC.
• Experience deploying front-end data analytics tools.
• Experience with distributed processing and querying solutions is a plus.
• Comfortable using Agile development methodologies and industry standard software development lifecycle processes (Jira, Git, documentation).
• Self-motivated individual with a strong desire to learn, explore, and excel in a fast-paced, innovative environment.

Responsibilities

• Develop and execute comprehensive verification strategies to validate complex digital designs, ensuring compliance with specifications and standards.
• Collaborate closely with design teams to understand design requirements and contribute to the creation of verification plans and testbenches.
• Write and execute test cases to verify functionality, performance, and power aspects of the design.
• Perform functional and formal verification to identify and debug design issues and ensure correct design behavior.
• Develop and maintain verification infrastructure, methodologies, and best practices to improve efficiency and productivity.
• Drive the adoption of advanced verification methodologies, tools, and techniques to enhance the overall verification process.
• Mentor and provide technical guidance to junior verification engineers, sharing expertise and best practices.
• Collaborate with cross-functional teams to analyze and resolve system-level issues and ensure seamless integration of the design.
• Stay updated with the latest industry trends, emerging technologies, and verification methodologies to drive innovation and continuous improvement.

Experience and Qualifications

• Bachelor's or Master's degree in Electrical/Computer Engineering or a related field.
• Proven experience as a Design Verification Engineer, with a focus on complex digital designs.
• Strong knowledge of digital design concepts, including RTL, synthesis, and timing constraints.
• Proficiency in verification methodologies such as UVM (Universal Verification Methodology) and SystemVerilog.
• Experience in developing and executing verification plans, testbenches, and test cases for digital designs.
• Solid understanding of functional coverage, assertion-based verification, and code coverage analysis.
• Proficiency in scripting and programming languages like Python, Perl, or C/C++.
• Familiarity with industry-standard EDA tools and simulation environments.
• Excellent problem-solving and debugging skills, with a keen eye for detail.
• Strong communication and interpersonal skills, with the ability to collaborate effectively in a team-oriented environment.
• Proven ability to work under tight deadlines and deliver high-quality results.

Responsibilities

• Collaborate with cross-functional teams to understand project requirements and translate them into effective AI solutions.
• Design, implement, and iterate on neural network architectures using PyTorch to achieve optimal performance on diverse tasks.
• Train, validate, and fine-tune machine learning models using relevant datasets to ensure high accuracy and robustness.
• Investigate and troubleshoot model performance issues, iterating on models and techniques to continuously improve results.
• Stay current with the latest research and developments in the field of machine learning and AI, applying relevant advancements to our projects.
• Contribute to the design and implementation of scalable and efficient AI pipelines.
• Work closely with engineers to integrate AI models into production systems.

Experience & Qualifications

• Bachelor's or higher degree in Computer Science, Engineering, or related field (or equivalent practical experience).
• Strong proficiency in Python programming and hands-on experience with PyTorch for developing and training deep learning models.
• Demonstrated experience in designing, training, and deploying neural networks for various applications.
• Solid understanding of machine learning fundamentals, including supervised and unsupervised learning techniques.
• Excellent problem-solving skills and the ability to approach challenges with creativity and a strong analytical mindset.
• Familiarity with debugging techniques and a knack for identifying issues and finding effective solutions.
• Experience with C++ is a plus but not mandatory.
• A self-motivated individual with a strong desire to learn, explore, and excel in a fast-paced, innovative environment.
• Strong communication skills and the ability to work collaboratively in a team setting.

Responsibilities

• Develop novel LLMs and primitives that take advantage of Tenstorrent’s breakthrough accelerator architecture to deliver orders of magnitude performance & efficiency improvements.
• Model benchmarking, Performance Analysis, Characterization on novel hardware accelerator.
• Fine tune/Retrain emerging LLM models after architectural modification to improve performance.
• Implement ideas from latest research papers and validate new optimizations on novel hardware, suggest improvements on the existing ideas and validate new ideas through experiments.
• Implement ML models on Tenstorrent’s PyBUDA Compiler framework and analyze results, suggest novel architectural changes to make them more efficient.

Experience & Qualifications

• Deep understanding of Transformer based model architecture (e.g., BERT, GPT, LLaMA, FALCON) - should be able to analyse performance bottlenecks in training or inference.
• Expertise (through evidence in prior projects or research) in large-scale foundation model (CNN/ Transformer/Generative) training and optimisations including quantisation, pruning, low-rank approximation (e.g., LoRA, SVD), sparsity aware training, early exit models, conditional computing, sparse attentions, NAS, fine-tuning (e.g., RLHF, PEFT)
• Excellent working knowledge of Python, PyTorch or TensorFlow, (optional C/C++ if interested in compiler and software stack)
• Familiarity with and passion for any of the following -- ML compilers, high-performance and massively parallel systems, distributed model training and inference, GPU or AI accelerator architecture -- is a plus.

Responsibilities

• Collaborate with cross-functional teams to design, implement, and optimize software components for AI acceleration platforms.
• Develop and maintain high-performance, low-level C++ code that interfaces with hardware accelerators.
• Work on compiler-related tasks, including code generation, optimization, and integration.
• Participate in code reviews to ensure code quality, maintainability, and performance.
• Debug and troubleshoot software and hardware integration issues.
• Keep up-to-date with industry trends and technologies related to AI and semiconductor development.
• Contribute to the continuous improvement of software development processes and practices.

Experience & Qualifications

• Bachelor's or Master's degree in Computer Science, Electrical Engineering, or a related field.
• Strong proficiency in C++ programming.
• Experience with compiler development and optimization is a strong plus.
• Knowledge of AI frameworks and hardware accelerators is advantageous.
• Familiarity with low-level programming and hardware-software co-design.
• Excellent problem-solving and debugging skills.
• Strong communication and teamwork abilities.
• Self-motivated with the ability to work independently and meet deadlines.

Responsibilities

• Translate end application use cases and workloads into systems and SoC architecture.
• Identify IP and determine make or buy; perform due-diligence as well as architect as appropriate.
• Write parts of relevant SoC specifications, iterate, and upkeep.
• Help to define APIs and SW/HW contracts and other co-design dependencies.
• Support direct end customer engagements that help to define use cases and system solutions.
• Support virtual and global engineering resources, including 3rd parties and joint ventures, in achieving business objectives.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering or Computer Science is required.
• 15+ years of proven Embedded Processor and Network SoC development experience – from inception to production.
• Software System architect who has hardware-software system co-design optimization experience in production bound design, especially in networking and I/O workloads.
• Direct working experiences with open-source platform distributions such as Linux, SONiC.
• Network protocol knowledge from Physical layer to the Transport layers, and kept up to date on the latest protocols, line speed, and various virtualization and acceleration techniques.
• Deep knowledge and experiences in the following relevant areas are desirable: (in their respective layers) Ethernet, IP/TCP/UDP, CPRI, TSN, AVTP, PTP, PSP, UEC, RoCE, Slingshot, HPC Ethernet, CAN-FD, AUTOSAR.
• High speed I/O sub-systems such as PCIe, CXL.io, CXL.mem, and storage and its transport such as NVMe, NVMeOF, Object, and Block storage.
• High speed network acceleration for both hardware termination and software termination and have insights to do either based on workload needs.
• Identity, Isolation, Security, and Privacy consequences at every HW layer.
• Experience with Software and hardware architecture co-design.
• Experience with AI Datapath integration in embedded SoC.

Responsibilities

• Decompose complete systems into application components and define services and APIs among the components. Help to adopt, buy, or develop strategies for the entire system components.
• Help or perform due-diligence of external IP selections on systems and software fitness.
• Write parts of relevant SoC specifications, Programming Model and Architecture, iterate, and upkeep.
• Help to define APIs and SW/HW contracts and other co-design dependencies.
• Optimize HW acceleration and workload for complete software defined networking, at 10 Gb/s ~ high-density 800Gb/s and beyond.
• Support direct end customer engagement that helps to define use cases and system solutions.
• Support virtual and global engineering resources, including 3rd parties and joint ventures, in achieving business objectives.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering or Computer Science is required.
• 15+ years of proven experience with connected applications and embedded systems – from inceptions to productions.
• Software Systems architect who understands HW/SW contracts, API and power-performance optimization, overall system performance scaling and optimization
• Hands-on experience with open source in networking operating systems is strongly preferred. (Ex: SONiC, Cumulus, OpenSwitch, etc)
• General familiarity of network protocol stacks, virtualization, hardware acceleration API that preserve software compatibility.
• Experience in the following relevant areas is desirable: (in their respective layers): Ethernet, IP/TCP/UDP, CPRI, TSN, AVTP, PTP, PSP, UEC, RoCE, Slingshot or HPC Ethernet.
• Familiarity with high speed I/O subsystems such as PCIe, CXL.io, CXL.mem, and storage subsystems such as NVMe, NVMeOF, Object, and Block storage.
• Experience with Identity, Isolation, Security, and Privacy consequences at every HW layer.
• Experience with Software and hardware architecture co-designAI Datapath integration in embedded SoC experience.

Responsibilities

• Kernel Development: Lead and participate in the design, development, and maintenance of kernel-level software components for our applications. develop and optimize kernels and kernel libraries for efficient machine learning and HPC applications.
• Implementation of tensor compute and tensor data movement optimizations kernels
• Heavy focus on optimizations.
• Low-Level Optimization: Analyze and optimize low-level code to improve the performance and efficiency of our software, with a strong emphasis on tensor optimization.
• Machine Learning Integration: Collaborate with machine learning engineers and data scientists to integrate optimized kernels and low-level routines into machine learning frameworks and pipelines.
• Performance Profiling: Identify performance bottlenecks, conduct performance profiling, and develop strategies to address and resolve them.
• Testing and Debugging: Write comprehensive unit tests, conduct thorough debugging, and ensure the stability and reliability of kernel-level code.
• Documentation: Create clear and concise documentation for code, APIs, and best practices to facilitate collaboration within the team.
• Research and Innovation: Stay up-to-date with the latest developments in kernel development, tensor optimization, and machine learning to propose innovative solutions and improvements.

Experience & Qualifications

• Bachelor's degree in Computer Science, Software Engineering, or a related field.
• Proven experience in kernel development, with a strong focus on low-level optimizations and tensor optimization.
• Proficiency in C/C++ programming languages.
• Familiarity with machine learning frameworks and concepts.
• Strong problem-solving skills and the ability to analyze and debug complex issues.
• Experience with performance profiling and optimization tools.
• Excellent communication and teamwork skills.
• Self-motivated, detail-oriented, and able to work independently as well as in a team.
• Experience with GPU programming (CUDA, OpenCL) is a plus.
• Knowledge of operating system internals is a plus.

Responsibilities

• Design, develop, and optimize system software for RISC-V-based AI and ML systems.
• Collaborate with cross-functional teams to define software requirements and specifications.
• Collaborate with the broader open-source community on shared solutions and contributions.
• Develop and maintain software stacks, including Operating Systems, drivers, firmware, and libraries, to support our hardware platforms.
• Implement and optimize system software, and contribute to AI/ML workload optimization.
• Participate in the HW/SW co-design and review process for architecture and products designs.
• Troubleshoot and resolve software and system-level issues.
• Develop and maintain software development processes, tools, and methodologies to ensure high-quality code and timely delivery.
• Stay up-to-date and engaged with the latest industry trends and advancements in RISC-V, AI, and ML technologies.

Experience & Qualifications

• Bachelor's degree or higher in Computer Science, Computer Engineering, Electrical Engineering, or a related field, or equivalent work experience.
• Strong debugging, problem-solving, and analytical skills.
• Excellent communication and teamwork abilities.
• Proven experience in delivering complex system software products to customers and internal stakeholders.
• 10+ years of professional experience in system software engineering.
• Solid understanding of RISC-V architecture and instruction set is a plus.
• Experience with product development of embedded software and real-time solutions is a plus.
• Strong coding skills in C/C++ and one or more of Python, Rust or Go.
• Familiarity with AI and ML algorithms, frameworks, and libraries.
• Experience with Linux kernel development and device driver programming.
• Experience with UEFI, EDK2/Tianocore and ACPI is a plus.
• Experience with AI accelerators and HW/SW co-design is a plus.

Responsibilities

• Design and layout of complex, 16+ layer PCBs, driving designs from concept through to production.
• Create and maintain schematic drawings, BOMs, and manufacturing files.
• Assist with simulation and extraction of board models for SI and PI.
• Generate wire harnessing drawings, as needed, for various projects.
• Collaborate with internal and external mechanical engineers to ensure PCB design compatibility with enclosures, thermal systems, and other mechanical components.
• Participate in design reviews, providing input on an area of expertise.
• Troubleshoot and resolve issues related to PCB design and layout, assemble and field failures.
• Document design processes and provide training to other team members as necessary.

Experience & Qualifications

• Bachelor's degree in Electrical Engineering or equivalent, with 5+ years of experience in the high speed digital field.
• Significant experience in mid to high speed PCB design and layout, at least 10Gbps (100GbE, GDDR6, PCIe Gen+, etc..).
• Architecture of multi-board solutions, connector selection and thermal impact a bonus.
• Experience with debugging radiated emissions and knowledge of best design practices to minimize emissions.
• Exposure to high speed performance, ICR, NEXT and FEXT an asset.
• Familiarity with mechanical design considerations and their application in PCB design.
• Proficiency with any of the main PCB ECAD tools, Altium preferred.
• Strong problem-solving skills and an ability to think critically.
• Excellent written and verbal communication skills.

Responsibilities

• Manage the monthly, quarterly, and annual financial close processes and ensure timely and accurate financial reporting
• Oversee the implementation and maintenance of SAP financial systems and processes
• Ensure compliance with GAAP accounting principles and other applicable accounting standards
• Manage the inventory accounting process, including valuation and reconciliation
• Prepare and review balance sheet reconciliations and journal entries
• Develop and implement internal controls to ensure accurate financial reporting and prevent fraud
• Work closely with cross-functional teams, including Operations, Sales, and Engineering to support business objectives
• Manage and develop a team of accounting professionals

Experience & Qualifications

• Bachelor's degree in Accounting or Finance; CPA certification required
• 7+ years of progressive accounting experience, with 2+ years in a lead or managerial role
• Extensive experience with GAAP accounting principles and SAP implementation
• Strong knowledge of inventory accounting and financial reporting
• Excellent analytical and problem-solving skills, with the ability to identify and resolve complex accounting issues
• Strong interpersonal and communication skills, with the ability to build and maintain effective working relationships with cross-functional teams
• Ability to manage multiple priorities in a fast-paced, dynamic environment

Responsibilities

• Manage the month-end and year-end closing processes, including journal entries, reconciliations, and financial statement preparation.
• Perform detailed account reconciliations to ensure accuracy and completeness of financial data.
• Prepare and review complex general ledger entries related to revenue recognition, expenses, and intercompany transactions.
• Collaborate with cross-functional teams to analyze financial data and provide insights to support decision-making.
• Assist in the development and implementation of accounting policies and procedures to ensure compliance with industry standards and regulations.
• Conduct regular financial analysis and variance analysis to identify trends and areas for improvement.
• Assist with the annual audit process by providing supporting documentation and answering auditor inquiries.
• Support the preparation of financial reports and presentations for senior management.
• Stay updated on accounting standards and regulations and ensure compliance with changes that may impact the organization.

Experience & Qualifications

• Bachelor's degree in Accounting, Finance, or related field; CPA certification is a plus.
• 5+ years of experience in general ledger accounting or related roles.
• Strong knowledge of US GAAP and accounting principles.
• Experience with accounting software and ERP systems, preferably in Quickbooks Online and/or SAP
• Excellent analytical and problem-solving skills with attention to detail.
• Ability to work independently and as part of a team in a fast-paced, dynamic environment.
• Effective communication skills, both written and verbal.
• Semiconductor, hardware or tech industry experience is a plus.
• Experience with revenue recognition and international accounting is a plus.

Responsibilities

• Lead and manage the global tax accounting function, including income tax, transfer pricing, and indirect tax compliance.
• Oversee the preparation and filing of tax returns, ensuring accuracy and compliance with local and international tax laws.
• Develop and maintain tax accounting policies and procedures to ensure alignment with accounting standards (e.g., ASC 740) and regulatory requirements.
• Collaborate with cross-functional teams to identify tax planning opportunities and risks associated with business operations and transactions.
• Provide guidance on tax implications of international expansion, mergers, acquisitions, and other strategic initiatives.
• Monitor changes in tax laws and regulations, assess their impact on the company, and implement necessary changes to ensure compliance.
• Prepare and review tax provisions and deferred tax calculations for financial reporting purposes.
• Manage relationships with external tax advisors, auditors, and tax authorities.
• Lead and mentor a team of tax professionals, fostering their growth and development.

Experience & Qualifications

• Bachelor's degree in Accounting, Finance, or related field; CPA and/or advanced tax qualification is preferred.
• 8+ years of progressive experience in tax accounting, including experience with international taxation.
• Strong knowledge of US GAAP and tax accounting principles (ASC 740).
• Proficiency in tax compliance software and ERP systems; experience with tax planning and provision software is a plus.
• Excellent understanding of international tax concepts, transfer pricing, and indirect taxes.
• Strong analytical and problem-solving skills, with attention to detail.
• Effective communication skills, both written and verbal.
• Ability to navigate complex tax regulations and adapt to changing tax landscapes.
• Leadership experience and the ability to manage and develop a team.

Responsibilities

• Manage daily cash operations, including cash forecasting, disbursements, and funding requirements.
• Develop and implement cash management strategies to optimize liquidity and maximize returns on excess cash.
• Monitor and analyze interest rates, foreign exchange rates, and other financial market indicators to inform investment decisions.
• Evaluate and recommend investment opportunities and financial instruments, such as short-term investments, money market funds, and certificates of deposit.
• Develop and maintain banking relationships, negotiating terms and conditions to ensure favorable terms for the organization.
• Identify and mitigate financial risks related to interest rate fluctuations, foreign exchange exposure, and credit risk.
• Ensure compliance with financial regulations and internal policies related to treasury operations.
• Prepare regular treasury reports and presentations for senior management and board meetings.
• Lead and mentor a team of treasury professionals, fostering their growth and development.

Experience & Qualifications

• Bachelor's degree in Finance, Accounting, or related field; Certified Treasury Professional (CTP) or other relevant certifications are a plus.
• 6+ years of experience in treasury roles, including cash management, investment, and risk management.
• Strong knowledge of treasury best practices, financial instruments, and investment strategies.
• Proficiency in treasury management systems and financial software.
• Excellent analytical and problem-solving skills, with attention to detail.
• Effective communication skills, both written and verbal.
• Ability to work independently and as part of a collaborative team.
• Experience in the semiconductor or tech industry is a plus.

Responsibilities

• Deployment, maintenance, support and monitoring of our infrastructure in the Bangalore office
• Act as sole onsite IT presence, therefore support and troubleshoot local technical issues from laptops to AV equipment
• Administration (of local and in part) of entire network- wide CentOS and Ubuntu Linux systems; systems security tasks including security scanning, patching and systems hardening
• Configure, add and maintain laptop, server, and network inventory including: firewall, Switches, and WiFi access points
• Partner with teammates ship across sites on various IT projects
• Onboarding of new employees at the Bangalore office by deploying necessary hardware and provisioning accounts
• Other task and duties as determined from time to time
• This role will have a physical as well as remote administration and support aspects

Required Qualifications

• Degree/diploma in Computer Science or demonstrated combination of education and experience
• 2+ years of Systems Administration experience in a small to mid-size company using Linux (CentOS/Redhat/Ubuntu)
• Linux+ certification
• 2+ years of installation and maintenance of enterprise level hardware, small deployments count provided its standard equipment
• 1+ years of experience with Network management, both physical infrastructure cabling and switches/firewall
• Experience with Veeam Back-ups or similar tools, managing backup & restoration implementation and testing
• Proficient with SNMP/Nagios/Managed Engine based Monitoring, ElasticSearch, Jamf and Grafana
• Worked with firewalls (Fortinet) and Linux based firewall (IPTABLES/IPCHAINS)
• Strong documentation abilities necessary to ensure timely problem resolution
• Experience with container orchestration systems (such as Kubernetes, Docker, Amazon ECS, EKS, Rancher)
• Skilled at managing cloud-based environments in AWS and Azure
• Proven ability to work autonomously with limited direction and oversight

Preferred Qualifications

• Network Administration with CCNA certification
• Administration experience with Office 365, and Google Workspace
• Strong technical problem-solving skills and experience in IP networking and static routing FTP, SSH, SMTP, DNS, HTTP/S, DHCP
• Python and other scripting languages such as bash, Ruby etc
• Intermediate knowledge of TCP/IP including the usage of stateful and stateless firewalls, access control lists, packet capture and logging, network design, Subnetting, IP routing, IPSEC virtual private networks, and intrusion detection and prevention
• Experience with automation/configuration management tools using Ansible, Chef or an equivalent
• Mac support and experience with Jamf is preferable

Responsibilities

• Develop, implement, and continuously improve Tenstorrent's global trade compliance program, covering customs matters, export controls, and sanctions
• Serve as primary point of contact and expert within the company on customs related topics, export controls and sanctions regulations, and coordinate with company departments to ensure compliance
• Implement policies, processes, and training to integrate trade compliance into our product development lifecycle
• Perform import and export classification of our technology and product portfolio, as well as any other items that may be imported or exported from time to time, in accordance with US and any other applicable regulations
• Apply for any applicable export licenses (including deemed exports) and classification requests, and evaluate and track the use of applicable license exceptions
• Maintain all import and export compliance documentation and records, consistent with regulatory requirements, and perform required reporting to government entities
• Conduct compliance reviews, assessments, and audits to identify potential issues and areas for improvement
• Perform restricted/denied party screening and resolve potential matches
• Establish and maintain relations with appropriate government regulatory agencies
• Generates performance metrics for import and export processes and continual compliance improvement

Experience & Qualifications

• B.A./B.S. or other relevant degree
• 5+ years of relevant working experience in technology industry and trade compliance, preferably at a start up
• Previous experience in the semiconductor industry
• Strong knowledge of EAR CCL Categories 3, 4, and 5
• Strong working knowledge of US export regulations, including the recently introduced regulations regarding artificial intelligence hardware, as well as sanctions and customs regulations
• Excellent organizational skills and attention to detail

Responsibilities

• Provide cross-functional legal advice to Leadership, Engineering, Product, HR/Recruiting, Sales, Software and Operations teams
• Draft, review and negotiate a variety of complex agreements including, but not limited to: leases, employment contracts, licensing agreements, NDA’s, MSA’s, SOW’s, SaaS, LOI’s, RMA’s, corporate governance documents, purchase agreements, terms and conditions and related paper
• Support business development and strategy teams involving Tenstorrent’s commercial partnerships
• Think creatively to address novel legal issues raised by modern semiconductor technology
• Monitor development in changes on industry specific regulations and legal matters, and provide advice on compliance with applicable laws and regulations while ensuring that appropriate risk management strategies are in place

Experience & Qualifications

• JD degree and state bar membership
• 4+ years experience in a law firm or in-house legal department
• Extensive experience working with startups, specifically in the semiconductor space and/or chip manufacturers or suppliers preferred
• Exceptional negotiation skills
• Experience providing solutions-oriented, practical legal advice to a variety of stakeholders
• Demonstrated excellence in analytical, written, and verbal communication
• Interpersonal skills and confidence to interact comfortably with employees at all levels of the organization including C-Suite
• Strong organizational skills, including ability to manage multiple simultaneous projects under deadline pressure
• Corporate transaction experience preferred