Responsibilities

• Define Design for Debug requirements for a from-scratch high performance and architect the overall debug capabilities and infrastructure
• Develop detailed microarchitecture for debug and trace logic for a server class CPU based on RISCV ISA
• RTL coding in Verilog leveraging on both industry tools as well as open-source infrastructure
• Work with design, test and post silicon validation teams to deploy debug features
• Drive trade-offs for your logic by working closely with performance, DV and physical design engineers to craft optimal solutions that meet the design goals
• Deploy innovative techniques for improving power, performance and area of the design, drive experiments with RTL and evaluate synthesis, timing and power results
• Debug RTL/logic issues across various hierarchies (core, chip) in both pre-silicon and post-silicon environment
• Enhance RTL design environment, tools and infrastructure

Experience & Qualifications

• BS/MS/PhD in EE/ECE/CE/CS with at least 5 years of experience
• Experience with Debug, Trace, JTAG and other design for debug (DFD) domains for an x86, ARM or RISCV based CPU
• Experience with computer architecture/system components/network/fabrics as a part of a CPU, ASIC or SOC design team
• Expertise in logic design and ability to evaluate functional, performance, timing and power for you design
• Strong experience with hardware description languages (Verilog, VHDL) and simulators (VCS, NC, Verilator)
• Expertise in microarchitecture definition and specification development
• Prior experience in industry standard ISAs – ARM, RISC-V, X86 preferred
• Strong problem solving and debug skills across various levels of design hierarchies