Responsibilities
- Lead pre-layout and post-layout simulation flow with a focus on high-speed interface and PDN, create simulation models and develop simulation methodology for SIPI design
- Lead SIPI validation methodology and develop detailed engineering test plans
- Model and optimize SI channel for PCBA, FPGA and ASIC on POD12 SE and SerDes interface standards
- Validate high speed interface and PDN impedance in lab to correlate simulation results and improve design flow
- Use simulation and lab data to support design troubleshooting and propose corrective actions, drive failure analysis, root cause efforts, and design of experiments to resolve problems
- Work with EE Board and Power design engineers, and ASIC design and verification engineers in collaborative cross functional teams to achieve project objectives
- Support multiple projects at the same time
Requirements
- MS EE or equivalent
- 5+ years of relevant SI/PI work experience in IT, HPC and/or AI hardware accelerator systems design
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Cerebras Systems has pioneered a groundbreaking chip and system that revolutionizes deep learning applications. Our system empowers ML researchers to achieve unprecedented speeds in training and inference workloads, propelling AI innovation to new horizons.
The Condor Galaxy 1 (CG-1), unveiled in a recent announcement, stands as a testament to Cerebras' commitment to pushing the boundaries of AI computing. With a staggering 4 ExaFLOP processing power, 54 million cores, and 64-node architecture, the CG-1 is the first of nine powerful supercomputers to be built and operated through an exclusive partnership between Cerebras and G42. This strategic collaboration aims to redefine the possibilities of AI by creating a network of interconnected supercomputers that will collectively deliver a mind-boggling 36 ExaFLOPS of AI compute power upon completion in 2024.
Cerebras is building a team of exceptional people to work together on big problems. Join us!